Advanced ASIC FPGA Engineer

Responsibilities for this Position

Advanced ASIC FPGA Engineer

ID: 2025-65501
USA-AZ-Scottsdale
Required Clearance: Top Secret, obtainable within reasonable time based on requirements
Posted Date: 2/20/2025
Category: Engineering-Hardware
Employment Type: Full Time
Hiring Company: General Dynamics Mission Systems, Inc.


Basic Qualifications

Bachelors degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 5 years of relevant experience; or Master's degree plus a minimum of 3 years of relevant experience.

CLEARANCE REQUIREMENTS: Department of DefenseTS/SCI security clearance ispreferred at time of hire. Candidates must be able to obtain a TS/SCI clearance within a reasonable amount of time from date of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.

Responsibilities for this Position

BASIC QUALIFICATIONS:

We encourage you to apply if you have any of these preferred skills or experiences:

• 3+ years experience verifying FPGAs or ASICSs
• In-depth experience using RTL simulation tools such as Siemens Mentor Graphics Questa or Modelsim tools or equivalent in a Linux Environment
• In-depth knowledge ofSystem Verilogobject orientedprogramming and theUniversal Verification Methodology (UVM).
• UnderstandsUVM TestbenchArchitectures
• Comfortable using and developing UVMagents, bus functionalmodels.
• Understands different types ofcoverage, usage of cover classes, cover points, etc.
• Experience with predictive testbench components,functional coverageandassertions.
• Experience withconstrained randomtesting.
• Experience with theRegister Abstraction Layer.
• Familiarity withrequirements-based verification, requirement tracing, and developing requirement verification strategies etc.
• Experience with scripting languages such as Linusshell scripts, TCL, Python.
• Familiarity with usingFormalVerification tools, code coverage, writing waivers etc.
• Familiarity with the following are also helpful
• Questa Verification IP (QVIP)
• Developing UVM testbenches for designs implemented inXilinxdevices with XilinxIPandSoCs
• AXIprotocols, PCIe, Space Wire, and Ethernet interfaces
• DSPfunctions and common signal processing components
• Familiar with debugging FPGA/ASIC hardware and assisting with HW/SW integration.
• Continuous Integration features ofGITLab.

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Duties and Tasks:
Responsible for definition, design, verification and documentation for ASIC (Application Specific Integrated Circuit) and/or FPGA (Field Programmable Gate Array) developments
Determines architecture, system simulation and detailed design approach
Defines module interfaces and all aspects of device design and simulation
Creates test and simulation plans that establish functional criteria
Verifies test results and analyzes performance
May also review vendor capabilities and simulation tools
Participates in the improvement of the ASIC/FPGA organizational processes
Supports the generation of technical engineering products by using the appropriate standards, processes, procedures, and tools throughout the ASIC/FPGA development life cycle
May provide leadership and/or direction to lower level employees
Independently determines approach to solutions
Contributes to the completion of major programs and projects
Plans and executes project tasks for activities described above

General Knowledge, Skills and Abilities:
This candidate must have an ability to operate in a team environment and learn new skills to accomplish the verification goals.
Proficient use and understanding of ASIC/FPGA engineering concepts, principles, and theories
Proficient in the principles and techniques of ASIC/FPGA design and the design process
Keeps abreast of technology trends
Proficient awareness of business objectives and Engineerings role in achieving
Proficient in Microsoft Office applications
Proficient written and verbal communications skills
Ability to think creatively
Ability to multi-task
Proficient skill in communicating issues, impacts, and corrective actions
Regular contact with senior levels of internal work groups
Works under limited direction
Contact with project leaders and other professionals within the Engineering department and with project teams across the company
Some contact with external customers

What sets you apart:

• Team player with strong communication skills, ability to lead verification of FPGA/ASICSs, and capacity to secure buy-in on concepts and ideas.
• Proficient with embedded micro-processing systems, FPGA Design and Verification using System Verilog, Verilog, and digital circuit analysis and design.
• Motivated to stay ahead of technology trends and drive innovation around design architectures, assembly, component selection, and electronics design.
• Creative thinker with high proficiency in technical problem solving and Research & Development experience.
• Commitment to ongoing professional development for yourself and others.

Our Commitment to You:

• An exciting career path with opportunities for continuous learning and development.
• Research oriented work, alongside award winning teams developing practical solutions for our nations security.
• Flexible schedules with every other Friday off work, if desired (9/80 schedule).
• Competitive benefits, including 401k matching, flex time off, paid parental leave, healthcare benefits, health & wellness programs, employee resource and social groups, and more.
• See more atgdmissionsystems.com/careers/why-work-for-us/benefits.

Workplace Options:
This position is fully on-site or hybrid/flex, as mutually agreed.
While on-site, you will be a part of theScottsdale, AZ team. Learn more athttps://gdmissionsystems.com/about-us/major-locations/scottsdale

Key Words: Verification, ASIC, FPGA, SystemVerilog, Verilog, Assertions (SVA), OVM, UVM, Digital Signal Processing (DSP), functional coverage, constrained random, formal verification, constrained random testing

#LI-Hybrid

#CJ1

Salary Note

This estimate represents the typical salary range for this position based on experience and other factors (geographic location, etc.). Actual pay may vary. This job posting will remain open until the position is filled.

Combined Salary Range

USD $116,811.40 - USD $129,587.60 /Yr.

Company Overview

General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation. With a global team of 12,000+ top professionals, we partner with the best in industry to expand the bounds of innovation in the defense and scientific arenas. Given the nature of our work and who we are, we value trust, honesty, alignment and transparency. We offer highly competitive benefits and pride ourselves in being a great place to work with a shared sense of purpose. You will also enjoy a flexible work environment where contributions are recognized and rewarded. If who we are and what we do resonates with you, we invite you to join our high-performance team!

Equal Opportunity Employer / Individuals with Disabilities / Protected Veterans

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